EQUALIZATION COMBINING OUTPUTS OF MULTIPLE COMPONENT FILTERS

摘要

An apparatus comprises read channel circuitry and associated signal processing circuitry. The signal processing circuitry comprises: an equalizer configured to combine an output of two or more component filters into a single equalized data signal; a detector with an input coupled to an output of the equalizer configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal; a decoder with an input coupled to an output of the detector configured to perform an iterative decoding process using the set of soft outputs, hard decision information and reliability indicators to determine a decoded data signal; and a multiplexer with a first input coupled to an output of the decoder, a second input coupled to an output of the detector, and an output coupled to an input of the equalizer. The hard decision information is used to train the equalizer.

主权项

1. An apparatus, comprising:
read channel circuitry; and signal processing circuitry associated with the read channel circuitry, the signal processing circuitry comprising:
an equalizer configured to combine an output of two or more component filters into a single equalized data signal;a detector with an input coupled to an output of the equalizer, the detector being configured to determine a set of soft outputs, hard decision information and reliability indicators of the single equalized data signal;a decoder with an input coupled to an output of the detector, the detector being configured to perform an iterative decoding process using the set of soft outputs, hard decision information and reliability indicators to determine a decoded data signal; anda multiplexer with a first input coupled to an output of the decoder, a second input coupled to an output of the detector, and an output coupled to an input of the equalizer; wherein the hard decision information is used to train the equalizer.