发明名称 INTELLIGENT INTERRUPT DISTRIBUTOR
摘要 An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.
申请公布号 US2014181351(A1) 申请公布日期 2014.06.26
申请号 US201213725698 申请日期 2012.12.21
申请人 NXP B.V. 发明人 Fatemi Hamed;Kapoor Ajay;Pineda de Gyvez Jose de Jesus;Escobar Juan Diego Echeverri
分类号 G06F13/40 主分类号 G06F13/40
代理机构 代理人
主权项 1. A multiprocessor system comprising: a first processor; a second processor coupled to the first processor by a first bus; a second bus coupled to the first bus; a clock gating unit directly coupled to the first processor and the second processor; a first and second peripheral device coupled to the second bus; and an intelligent interrupt distributor coupled to the first bus and directly coupled to the first and second processor by an interrupt bus and directly coupled to the first and second peripheral device by a first and second peripheral interrupt line and directly coupled to the clock gating unit such that an interrupt received on the first or the second peripheral interrupt line is distributed via the interrupt line to one of the first and the second processors which is in an idle state.
地址 Eindhoven NL