| 摘要 |
In a Low Density Parity Check (LDPC) scheme for decoding communication channels, interleavers 710 are used to perform mappings A which determine the positions of positive bit values (ie. ones) in a a sparse (ie. primarily zero) parity check matrix H (Fig. 5A). For each of a number of data vectors d=(d1, d2 ... dk), an encoder (420, fig. 4A) outputs a linear block of code vectors c=(c1, c2 ... cn) such that c∙HT=0 and n>k (ie. n-k parity bits are generated). A generator matrix G may be formed from an identity matrix I and a parity submatrix P (fig. 6), its rows being code vectors c. An address r corresponds to a column index of P (ie. a row index of H) which an interleaver maps to a second address A1..W[r] which selects and retrieves particular bits of d from a memory 730 before calculating a parity check bit p[r] = (d[A1[r]] + ... + d[AW[r]]) mod 2. Code vector c=(d│p) is then transmitted, and received code block c=c+e is decoded (470, fig 4B) to yield received data vectors d which are set equal to d if the parity check is successful. |
