Hierarchical equivalence checking and efficient handling of equivalence checks when engineering change orders are in an unsharable register transfer level

摘要

An apparatus, a hierarchical method of equivalence checking a circuit design and equivalency checking after engineering change orders in a circuit design are disclosed herein. In one embodiment, a method of equivalence checking includes: (1) receiving a post-engineering change order (ECO) netlist of a first one of the functional blocks, wherein the post-ECO netlist has been verified employing an equivalence checker, (2) generating a top level netlist for the circuit design including the post-ECO netlist and a block netlist for a second one of the multiple functional blocks, (3) generating a top level register transfer level (RTL) for the circuit design including a RTL for the second functional block and (4) performing an equivalency check of the top level RTL to the top level netlist, wherein a RTL for the first functional block and the post-ECO netlist are black boxed for the performing.

主权项

1. A method of equivalence checking a top level of a circuit design having multiple functional blocks, comprising:
receiving, by a computer, a post-engineering change order (ECO) netlist of a first one of said functional blocks, wherein said post-ECO netlist has been verified employing an equivalence checker; generating a top level netlist for said circuit design including said post-ECO netlist and a block netlist for a second one of said multiple functional blocks; generating a top level register transfer level (RTL) for said circuit design including a RTL for said second functional block; and performing an equivalency check of said top level RTL to said top level netlist, wherein a RTL for said first functional block and said post-ECO netlist are black boxed for said performing, wherein said black boxed RTL for said first functional block is analyzed as a whole without examining internal circuitry thereof.