Vertical nanowire based hetero-structure split gate memory

摘要

A memory cell is disclosed. The memory cell includes a vertical base disposed on a substrate. The vertical base includes first and second channels between top and bottom terminals. The memory cell also includes a first gate surrounding the first channel and a second gate surrounding the second channel. The first and second gates form a gate-all-around transistor of the memory cell.

主权项

1. A memory cell comprising:
a vertical base disposed on a substrate, the vertical base includes first and second channels between top and bottom terminals; a first gate surrounding the first channel; and a second gate surrounding the second channel, wherein the first and second gates form a gate-all-around transistor of the memory cell.