发明名称 |
Semiconductor package and package on package having the same |
摘要 |
A semiconductor package and a package on package are provided. The semiconductor package includes a substrate; a semiconductor chip attached to a surface of the substrate; connecting conductors disposed on the surface of the substrate; a mold formed on the substrate and in which the connecting conductors and the semiconductor chip are provided; and connecting via holes extending through the mold and exposing the connecting conductors. With respect to a first connecting via hole of the connecting via holes, a planar distance between a first connecting conductor exposed by the first connecting via hole and an entrance of the first connecting via hole is not uniform. |
申请公布号 |
US8759967(B2) |
申请公布日期 |
2014.06.24 |
申请号 |
US201314013238 |
申请日期 |
2013.08.29 |
申请人 |
Samsung Electronics Co., Ltd. |
发明人 |
Byun Hak-Kyoon;Choi Dae-Young;Kim Mi-Yeon |
分类号 |
H01L23/02;H01L23/48 |
主分类号 |
H01L23/02 |
代理机构 |
Sughrue Mion, PLLC |
代理人 |
Sughrue Mion, PLLC |
主权项 |
1. A semiconductor package comprising:
a substrate; a semiconductor chip attached to a surface of the substrate; a plurality of connecting conductors; and a mold formed on the substrate for holding the semiconductor chip and comprising a plurality of via holes which expose corresponding ones of the connecting conductors through the mold, wherein, for a first via hole of the plurality of via holes, a planar distance between a connecting conductor exposed by the first via hole and an entrance of the first via hole is not uniform.
|
地址 |
Suwon-Si KR |