发明名称 |
Memory component that samples command/address signals in response to both edges of a clock signal |
摘要 |
A memory component has a signaling interface, data input/output (I/O) circuitry and command/address (CA) circuitry. The signaling interface includes an on-die terminated data I/O and an unterminated CA input. The data I/O circuitry is dedicated to sampling write data bits at the data I/O timed by a strobe signal and to transmitting read data bits timed by a first clock signal, each of the write and read data bits being valid for a bit time at the data I/O. The CA circuitry samples CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component. |
申请公布号 |
US8760944(B2) |
申请公布日期 |
2014.06.24 |
申请号 |
US201313923656 |
申请日期 |
2013.06.21 |
申请人 |
Rambus Inc. |
发明人 |
Ware Frederick A.;Tsern Ely K.;Perego Richard E.;Hampel Craig E. |
分类号 |
G11C7/00 |
主分类号 |
G11C7/00 |
代理机构 |
|
代理人 |
Shemwell Charles |
主权项 |
1. A memory component comprising:
a signaling interface having an on-die terminated data input/output (I/O), an unterminated input to receive command/address (CA) signals and a strobe input, each to be coupled to a respective external signaling link; data I/O circuitry dedicated to (i) sampling write data bits at the data I/O, the sampling of the write data bits being timed by a strobe signal received via the strobe input, and (ii) transmitting read data bits timed by a first clock signal, each of the write data bits and read data bits being valid for a respective bit time at the data I/O; and CA circuitry to sample CA signals at the CA input in response to both rising-edge and falling-edge transitions of a second clock signal, the CA signals indicating read and write operations to be performed within the memory component with regard to the read data bits and write data bits, respectively.
|
地址 |
Sunnyvale CA US |