SINGLE LAYER CORELESS SUBSTRATE

摘要

The present invention relates to an electronic chip package and a method for manufacturing the electronic chip package. The electronic chip package includes at least one chip bonded to a routing layer of an interposer having a routing layer and a via post layer which is surrounded by a dielectric material with glass fibers in a polymer matrix and also includes a second layer of a dielectric material encapsulating the at least one chip, the routing layer, and a wire.