| 摘要 |
<p>Disclosed is an on-chip clock control circuit for an at-speed test of a system on-chip. The on-chip clock control circuit comprises a clock control chain and at least one or more domain clock generators. The clock control chain shifts clock control bits in series in response to a clock control scan clock supplied from the outside a chip and respectively outputs the clock control bits corresponding to at least one or more clock domains. Each of the domain clock generators selectively outputs a corresponding data scan clock in at least one or more data scan clocks supplied from the outside the chip and a corresponding function clock in at least one or more function clocks in the inside the chip in a test mode in response to the clock control bits, and generates the data scan clock and the function clock as internal clocks. Therefore, the clock control chain and the operation clocks of the clock generator are supplied independently from each other, thereby preventing unnecessary power consumption due to toggling of flip-flop.</p> |
