ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWIRES AND SUBSTRATE SURFACE

摘要

A method of forming a semiconductor device is provided. The method includes providing a structure including, a handle substrate, a buried boron nitride layer located above an uppermost surface of the handle substrate, a buried oxide layer located on an uppermost surface of the buried boron nitride layer, and a top semiconductor layer located on an uppermost surface of the buried oxide layer. Next, a first semiconductor pad, a second semiconductor pad and a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration are patterned into the top semiconductor layer. The semiconductor nanowires are suspended by removing a portion of the buried oxide layer from beneath each semiconductor nanowire, wherein a portion of the uppermost surface of the buried boron nitride layer is exposed. Next, a gate all-around field effect transistor is formed.

主权项

1. A semiconductor device comprising:
a first buried oxide layer portion and a second buried oxide layer portion each located on an uppermost surface of a buried boron nitride layer, wherein a portion of said uppermost surface of said buried boron nitride layer between said first and second buried oxide layer portions is exposed; a first semiconductor pad located atop said first buried oxide layer portion; a second semiconductor pad located atop said second buried oxide layer portion; a plurality of semiconductor nanowires connecting the first semiconductor pad and the second semiconductor pad in a ladder-like configuration and suspended above said exposed portion of said uppermost surface of said buried boron nitride layer; a gate dielectric surrounding each semiconductor nanowire and located directly on a top surface and a bottom surface of each semiconductor nanowire; a gate surrounding each semiconductor nanowire and located directly on a surface of each gate dielectric; and a gate dielectric portion located directly on a surface of said exposed portion of said buried boron nitride layer, and in contact with a surface of said gate located beneath each semiconductor nanowire.