DECODER CIRCUIT WITH REDUCED CURRENT LEAKAGE

摘要

A decoder circuit with reduced leakage configured to decode an address and drive one of a number of word lines may be implemented with two-high logic gates in a pre-decode stage, a decode stage, and a word line driver stage. Such decoder circuits may include, in the word line driver stage, a number of two-high NOR gates configured to drive one of a number of word lines. In some embodiments, the two-high logic gates that share common inputs are implemented with multi-output static logic.

主权项

1. A decoder circuit comprising:
a decode stage configured to decode a plurality of decode input signals into a plurality of word line driver input signals; and a word line driver stage configured to drive a plurality of word lines, wherein the word line driver stage comprises a plurality of two-high NOR gates, each two-high NOR gate configured to receive two of the word line driver input signals and drive a word line based on the word line driver input signals.