LINK CLOCK CHANGE DURING VERITCAL BLANKING

摘要

Embodiments of an apparatus for implementing a display port interface are disclosed. The apparatus may include a source processor and a sink processor coupled through an interface. The interface may include a primary link, and an auxiliary link. The source processor may be operable to send a wake-up command to the sink processor via the auxiliary link, which may indicate a change in frequency on the primary link. The source processor to the sink processor via the primary link may send initialization parameters, which may include a clock data recovery lock parameter and an idle parameter.

主权项

1. An apparatus, comprising:
a source processor; and a sink processor coupled to the source processor through a primary link, and an auxiliary link; wherein the source processor is configured to:
send a wake-up command to the sink processor via the auxiliary link, wherein the wake-up command indicates a change in frequency on the primary link; andsend a plurality of initialization parameters to the sink processor via the primary link; wherein the plurality of initialization parameters include a clock data recovery lock parameter, and an idle parameter.