发明名称 FEC DECODER DYNAMIC POWER OPTIMIZATION
摘要 A computing device is configured to analyze a logic gate design having logic gates. The computing device is configured further to identify logic gates that are affected by toggling activity associated with an input of one or more of the logic gates. The computing device is configured further to replace, within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity; and output a new logic gate design based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, producing a same output as the application specific integrated circuit with the logic gate design, based on same inputs.
申请公布号 US2014173538(A1) 申请公布日期 2014.06.19
申请号 US201213719893 申请日期 2012.12.19
申请人 ADAVANI Vinay 发明人 ADAVANI Vinay
分类号 G06F17/50 主分类号 G06F17/50
代理机构 代理人
主权项 1. A method comprising: analyzing, by a computing device, a logic gate design, of an application specific integrated circuit, having a plurality of logic gates; identifying, by the computing device, logic gates, of the plurality of logic gates, that are affected by toggling activity associated with an input of one or more of the plurality of logic gates; replacing, by the computing device and within the logic gate design, the identified logic gates with different logic gates that are not affected by the toggling activity, a quantity of the different logic gates being smaller than a quantity of the identified logic gates; and outputting, by the computing device, a new logic gate design for the application specific integrated circuit based on replacing the identified logic gates with the different logic gates, the application specific integrated circuit, with the new logic gate design, consuming less power than the application specific integrated circuit with the logic gate design.
地址 Koramangala IN