发明名称 |
Build-up package for integrated circuit devices, and methods of making same |
摘要 |
A device is disclosed which includes, in one illustrative example, an integrated circuit die having an active surface and a molded body extending around a perimeter of the die, the molded body having lips that are positioned above a portion of the active surface of the die. Another illustrative example includes an integrated circuit die having an active surface, a molded body extending around a perimeter of the die and a CTE buffer material formed around at least a portion of the perimeter of the die adjacent the active surface of the die, wherein the CTE buffer material is positioned between a portion of the die and a portion of the molded body and wherein the CTE buffer material has a coefficient of thermal expansion that is intermediate a coefficient of thermal expansion for the die and a coefficient of thermal expansion for the molded body. |
申请公布号 |
US8754537(B2) |
申请公布日期 |
2014.06.17 |
申请号 |
US201113182069 |
申请日期 |
2011.07.13 |
申请人 |
Micron Technology, Inc. |
发明人 |
Ng Hong Wan;Lee Choon Kuan;Corisis David J.;Chong Chin Hui |
分类号 |
H01L23/29 |
主分类号 |
H01L23/29 |
代理机构 |
Perkins Coie LLP |
代理人 |
Perkins Coie LLP |
主权项 |
1. A device, comprising:
an integrated circuit die having an active surface, a backside, and bond pads at the active side, wherein the bond pads have a contact surface facing away from the die; a coefficient of thermal expansion (CTE) buffer material formed at a perimeter of the die and at least substantially coplanar with the active surface; and a molded body extending around the perimeter of the die and around the CTE buffer material, wherein at least a portion of the molded body is in direct contact with at least a portion of the perimeter of the die; wherein the die has a first CTE, the molded body has a second CTE different from the first CTE, and the CTE buffer material has a third CTE intermediate to the first CTE and the second CTE; wherein the CTE buffer material has a triangular cross-section; and wherein the integrated circuit die has a sidewall contacting the CTE buffer, and wherein the CTE buffer material has a first leg generally parallel with the sidewall and contacting approximately half the sidewall, a second leg generally coplanar with the active surface of the integrated circuit die, and a third leg extending between the first leg and the second leg.
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地址 |
Boise ID US |