Multi-chip wafer level package

摘要

A multi-chip wafer level package comprises three stacked semiconductor dies. A first semiconductor die is embedded in a first photo-sensitive material layer. A second semiconductor die is stacked on top of the first semiconductor die wherein the second semiconductor die is face-to-face coupled to the first semiconductor die. A third semiconductor die is back-to-back attached to the second semiconductor die. Both the second semiconductor die and the third semiconductor die are embedded in a second photo-sensitive material layer. The multi-chip wafer level package further comprises a plurality of through assembly vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.

主权项

1. A device comprising:
a first semiconductor die embedded in a first photo-sensitive material layer; a second semiconductor die stacked on top of the first semiconductor die, wherein the second semiconductor die is face-to-face coupled to the first semiconductor die; a second photo-sensitive material layer formed on top of the first photo-sensitive material layer, wherein the second semiconductor die is embedded in the second photo-sensitive material layer; a dielectric layer directly in contact and between the first photo-sensitive material layer and the second photo-sensitive material layer, wherein a plurality of first vias formed between the first semiconductor die and the second semiconductor die and the first vias are formed in the first photo-sensitive material layer, and wherein a plurality of second vias formed in the dielectric layer and each second via is vertically aligned with a corresponding first via and a redistribution line is formed between the second via and the corresponding first via; and a plurality of through vias formed in the first photo-sensitive material layer and the second photo-sensitive material layer.