Method and apparatus for programmable coupling between CPU and co-processor

摘要

In one embodiment the present invention includes a method and apparatus for enabling a main core and one or more co-processors to operate in a de-coupled mode, thereby facilitating the execution of two or more instruction threads in parallel. A co-processor, according to an embodiment of the invention, has a coupling manager including a loop buffer for storing instructions which can be independently fetched and executed by the co-processor when operating in de-coupled mode. In addition, the coupling manager includes a loop descriptor and a counter/condition descriptor. The loop descriptor and condition descriptor work in conjunction with one another to determine what, if any, action should be taken when a co-processor is in a particular processing state, for example, as indicated by a counter keeping track of loop processing.

主权项

1. A method for processing data, comprising:
identifying one or more instructions by a main core; loading, by the main core, a loop buffer of a co-processor with the one or more instructions of a first instruction thread for the co-processor to execute the one or more instructions independent of the main core in a first mode, the main core and the co-processor being decoupled in the first mode; simultaneously executing a second instruction thread at the main core while the co-processor executes the one or more instructions loaded into the loop buffer while in the first mode; verifying that the co-processor is available based on a first state of a flap; changing a mode of operation of the co-processor from the first mode to a second mode when the co-processor completes the execution of the one or more instructions, the decoupled main core and co-processor being re-coupled in the second mode; and setting the flag to a second state.