System and Method for Accelerating and Decelerating Packets

摘要

In one embodiment, a system for accelerating a packet stream includes a first accelerator configured to re-clock the packet stream from a first clock rate to a second clock rate to produce an accelerated packet stream, where the first clock rate is less than the second clock rate, where the packet stream has a first inter-packet gap, where the accelerated packet stream has a second inter-packet gap, and where the second inter-packet gap is greater than the first inter-packet gap. The system also includes a switch coupled to the first accelerator, where the switch is configured to switch the accelerated packet stream at the second clock rate to produce a switched packet stream.

主权项

1. A system for accelerating a packet stream, the system comprising:
a first accelerator configured to re-clock a plurality of input packets of the packet stream from a first clock rate to a second clock rate to produce a plurality of accelerated packets of an accelerated packet stream, wherein the first clock rate is less than the second clock rate, wherein a first plurality of leading edges of the plurality of input packets is synchronous with a second plurality of leading edges of the plurality of accelerated packets, wherein the packet stream has a first inter-packet gap, wherein the accelerated packet stream has a second inter-packet gap, and wherein the second inter-packet gap is greater than the first inter-packet gap; and a switch coupled to the first accelerator, wherein the switch is configured to switch the accelerated packet stream at the second clock rate to produce a switched packet stream.