PARTIAL SOI ON POWER DEVICE FOR BREAKDOWN VOLTAGE IMPROVEMENT

摘要

The present disclosure relates to a method and apparatus to increase breakdown voltage of a semiconductor power device. A bonded wafer is formed by bonding a device wafer to a handle wafer with an intermediate oxide layer. The device wafer is thinned substantially from its original thickness. A power device is formed within the device wafer through a semiconductor fabrication process. The handle wafer is patterned to remove section of the handle wafer below the power device, resulting in a breakdown voltage improvement for the power device as well as a uniform electrostatic potential under reverse biasing conditions of the power device, wherein the breakdown voltage is determined. Other methods and structures are also disclosed.

主权项

1. A power device, comprising:
a transistor disposed on a first surface of a device wafer and including a source region, a drain region, and a channel region which are laterally spaced apart over the first surface; and a handle wafer bonded to a second surface of the device wafer with an intermediate oxide layer, the handle wafer comprising: an un-recessed region having a first handle wafer thickness under the source region, and a recessed region having a second handle wafer thickness under both the channel region and the drain region, the second wafer thickness being less than the first wafer thickness.