发明名称 |
MEMORY ARCHITECTURE FOR DISPLAY DEVICE AND CONTROL METHOD THEREOF |
摘要 |
A memory architecture for a display device and a control method thereof are provided. The memory architecture includes a display data memory and a memory controller. The display data memory includes N sub-memories and N×M arbiters, wherein N is a positive integer and M is a positive integer equal to or greater than 2. Each sub-memory includes M memory blocks divided by an address. Each M arbiters are coupled to the M memory blocks of each sub-memory. The memory controller, coupled to the N×M arbiters, generates N×M sets of request signals and output address signals according to a set of an input request signal and an input address signal, and transmits to the N×M arbiters to sequentially control the N×M arbiters. |
申请公布号 |
US2014164691(A1) |
申请公布日期 |
2014.06.12 |
申请号 |
US201414181162 |
申请日期 |
2014.02.14 |
申请人 |
NOVATEK MICROELECTRONICS CORP. |
发明人 |
LAI Ching-Wen;HO Hsi-Chi |
分类号 |
G11C11/406 |
主分类号 |
G11C11/406 |
代理机构 |
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代理人 |
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主权项 |
1. A memory apparatus, comprising:
a memory having N sub-memories, each of the sub-memory having M memory blocks, N being a positive integer, M being a positive integer; N×M arbiters respectively coupled to N×M memory blocks; and a memory controller, coupled to the N×M arbiters, for generating N×M sets of output request signals and output address signals according to an input signal set of an input request signal and an input address signal, and transmitting to the N×M arbiters, wherein a cycle period of each of the N×M output request signals is longer than a cycle period of the input request signal.
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地址 |
Hsinchu TW |