Error check-only mode

摘要

Video display pipes may terminate with a FIFO (first-in first-out) buffer from which pixels are provided to a display controller to display the pixels on a graphics/video display. The display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the FIFO buffer. In an error-checking only mode, the FIFO may be disabled, and an error-checking (e.g. CRC) block connected in front of the FIFO may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels. Accordingly, the length of test/simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels. It also becomes possible to perform testing/simulation in environments where a display is not supported or is not available. The results generated by the error-checking may be read and compared to an expected value to detect test pass/fail conditions.

主权项

1. A graphics processing display pipe comprising:
one or more processing blocks configured to process pixels and produce output pixels from the processed pixels; a buffer configured to:
store the output pixels for reading by a display controller during a first mode of operation of the display pipe; andnot store the output pixels during a second mode of operation of the display pipe; and an error-checking block configured to receive the output pixels during the second mode of operation, and compute an error-checking value corresponding to the output pixels during the second mode of operation at a rate commensurate with a rate at which the one or more processing blocks process the pixels; wherein during the first mode of operation of the display pipe, the buffer is enabled to allow the buffer to receive and store the output pixels produced by the one or more processing blocks; and wherein during the second mode of operation of the display pipe the buffer is disabled to allow the error-checking block to receive the output pixels at a rate at which the one or more processing block as producing the output pixels.