Nonvolatile semiconductor memory

摘要

A memory includes first and second select gate transistors, memory cells, a source line, a bit line, a selected word line which is connected to a selected memory cell as a target of a verify reading, a non-selected word line which is connected to a non-selected memory cell except the selected memory cell, a potential generating circuit for generating a selected read potential which is supplied to the selected word line, and generating a non-selected read potential larger than the selected read potential, which is supplied to the non-selected word line, and a control circuit which classifies a threshold voltage of the selected memory cell to one of three groups by verifying which area among three area which are isolated by two values does a cell current of the selected memory cell belong, when the selected read potential is a first value.

主权项

1. A nonvolatile semiconductor memory comprising:
a first transistor; a second transistor; a memory cell unit including memory cells electrically connected in series between the first transistor and the second transistor; a source line electrically connected to the first transistor; a bit line electrically connected to the second transistor; word lines electrically connected to gates of the memory cells; a sense amplifier including a first node, a third transistor, a fourth transistor and a first capacitor, one end of the third transistor being electrically connected to the bit line, another end of the third transistor being electrically connected to the first node, one end of the fourth transistor being electrically connected to both the first node and the other end of the third transistor, and one end of the first capacitor being electrically connected to the first node; and a controller configured to perform a verify operation on a condition that a verify voltage is applied to a first word line selected from the word lines, the verify operation including a first operation and a second operation, to apply a first voltage to a gate of the fourth transistor and apply a second voltage to a gate of the third transistor in the first operation, and to apply a third voltage to the gate of the fourth transistor and apply a fourth voltage to the gate of the third transistor in the second operation, the second voltage being higher than the first voltage and the fourth voltage being higher than the third voltage.