Backlight brightness control for liquid crystal display panel using a frequency-divided clock signal

摘要

A display device is provided with a display panel on which a plurality of display pixels are provided; a backlight illuminating the display panel; and a display panel driver driving the display panel. The display panel driver externally receiving image data and a clock signal for controlling timings of receiving the image data. The display panel driver includes a backlight controller generating a PWM-modulated drive signal to drive the backlight. The frequency of the PWM-modulated drive signal is dependent on a frequency-divided clock signal generated by frequency dividing of the clock signal externally received. The frequency-divided clock signal is generated so that the frequency of the PWM-modulated drive signal is kept constant when the frequency of the clock signal externally received is switched.

主权项

1. A display device comprising:
a display panel on which a plurality of display pixels are provided; a backlight illuminating said display panel; and a display panel driver driving said display panel, wherein said display panel driver externally receives image data and a clock signal for controlling timings of receiving said image data, wherein said display panel driver includesa backlight controller generating a Pulse Width Modulation (PWM)-modulated drive signal to drive said backlight, wherein said display panel driver externally receives vertical and horizontal sync signals, and said clock signal externally received by said display panel driver comprises a dot clock signal, wherein said display panel driver further includes:
a size recognition circuit which performs automatic size recognition processing to recognize a horizontal resolution of said image data in response to said dot clock signal and said vertical and horizontal sync signals in a vertical back porch period;a horizontal enlargement circuit adapted to implement a horizontal image enlargement on said image data to generate enlarged image data in response to said recognized horizontal resolution; anda display panel control section adapted to drive said display panel in response to said enlarged image data, wherein a frequency of said PWM-modulated drive signal is dependent on a frequency-divided clock signal generated by frequency dividing of said dot clock signal externally received, and wherein said size recognition circuit generates said frequency-divided clock signal in response to said recognized horizontal resolution so that said frequency of said PWM-modulated drive signal is kept constant when a frequency of said dot clock signal externally received is switched.