| 摘要 |
An apparatus is provided that compensates for misalignment on a synchronous data bus. The apparatus includes a Joint Test Action Group (JTAG) interface, a synchronous bus optimizer, and a delay-locked loop (DLL). The JTAG interface is configured to receive control information over a standard JTAG bus, where the control information indicates an amount to delay a data bit signal associated with a data group. The synchronous bus optimizer is configured to receive the control information, and is configured to develop a value on a ratio bus that indicates the amount. The DLL is coupled to the ratio bus, and is configured generate a delayed data bit signal, where the DLL adds the amount of delay to the data bit signal to generate the delayed data bit signal. |
| 主权项 |
1. An apparatus that compensates for misalignment on a synchronous data bus, the apparatus comprising:
a receiving device, comprising:
a Joint Test Action Group (JTAG) interface, configured to receive control information over a standard JTAG bus, wherein said control information indicates a first amount to delay a data bit signal relative to a synchronous data strobe signal associated with a data group; a synchronous bus optimizer, configured to receive said control information, and configured to develop a value on a first ratio bus that indicates said first amount; and a delay-locked loop (DLL), coupled to said first ratio bus, configured generate a delayed data bit signal, wherein said DLL adds said first amount of delay to said data bit signal to generate said delayed data bit signal; and a transmitting device, coupled to said receiving device, said transmitting device comprising:
a core clocks generator, coupled to a second ratio bus, configured to advance a data strobe clock by a second amount, said core clocks generator comprising:
a phase locked loop (PLL), comprising:PLL forward elements, configured to receive a bus clock signal, and configured to generate said data strobe clock signal at a frequency multiple of said bus clock signal;a second delay-locked loop (DLL), configured to receive said data strobe clock signal and said second ratio bus, and configured to generate an output that comprises said data strobe clock signal delayed by said second amount; anda frequency divider, configured to receive said output, and configured to generate a delayed reference signal to enable said PLL forward elements to align said output in phase with said bus clock signal, thereby causing said data strobe clock signal to be advanced by said second amount; and a synchronous strobe driver, configured to receive said data strobe clock signal, and configured to employ said data strobe clock signal to generate said synchronous data strobe signal, wherein said synchronous data strobe signal, when enabled, is advanced also by said second amount.
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