发明名称 |
Method and apparatus for minimizing cache conflict misses |
摘要 |
A method for minimizing cache conflict misses is disclosed. A translation table capable of facilitating the translation of a virtual address to a real address during a cache access is provided. The translation table includes multiple entries, and each entry of the translation table includes a page number field and a hash value field. A hash value is generated from a first group of bits within a virtual address, and the hash value is stored in the hash value field of an entry within the translation table. In response to a match on the entry within the translation table during a cache access, the hash value of the matched entry is retrieved from the translation table, and the hash value is concatenated with a second group of bits within the virtual address to form a set of indexing bits to index into a cache set. |
申请公布号 |
US8751751(B2) |
申请公布日期 |
2014.06.10 |
申请号 |
US201113015771 |
申请日期 |
2011.01.28 |
申请人 |
International Business Machines Corporation |
发明人 |
Bell, Jr. Robert H.;Chiang Men-Chow;Hua Hong L. |
分类号 |
G06F12/00;G06F12/08;G06F12/10 |
主分类号 |
G06F12/00 |
代理机构 |
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代理人 |
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主权项 |
1. A method for minimizing cache conflict misses, said method comprising:
providing a translation table having a plurality of entries, wherein each entry includes a page number field and a hash value field; generating a hash value from a first group of bits within a virtual address; storing said hash value in said hash value field of an entry within said translation table; and in response to a match on said entry within said translation table during a cache access, retrieving said hash value of said matched entry from said translation table, and concatenating said hash value with a second group of bits within said virtual address to form a set of indexing bits to index into a cache set.
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地址 |
Armonk NY US |