发明名称 Integrated circuit having silicide block resistor
摘要 A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor) includes forming a dielectric isolation region in a top semiconductor surface of a substrate. A polysilicon layer is formed including patterned resistor polysilicon on the dielectric isolation region and gate polysilicon on the top semiconductor surface. Implanting is performed using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon and gate polysilicon of a MOS transistor with at least a first dopant. Implanting is then performed using a second shared MOS/resistor polysilicon implant level for simultaneously implanting the patterned resistor polysilicon, gate polysilicon and source and drain regions of the MOS transistor with at least a second dopant. A metal silicide is formed on a first and second portion of a top surface of the patterned resistor polysilicon to form the SIBLK poly resistor.
申请公布号 US8748256(B2) 申请公布日期 2014.06.10
申请号 US201213366903 申请日期 2012.02.06
申请人 Texas Instruments Incorporated 发明人 Zhao Song;Baldwin Gregory Charles;Ekbote Shashank S.;Choi Youn Sung
分类号 H01L27/088 主分类号 H01L27/088
代理机构 代理人
主权项 1. A method for forming an integrated circuit (IC) including a silicide block poly resistor (SIBLK poly resistor), comprising: forming an dielectric isolation region in a top semiconductor surface of a substrate; forming a polysilicon layer including a patterned polysilicon resistor disposed entirely on said dielectric isolation region and gate polysilicon on a gate dielectric on said top semiconductor surface; implanting using a first shared metal-oxide-semiconductor (MOS)/resistor polysilicon implant level for simultaneously implanting said patterned polysilicon resistor and said gate polysilicon of a MOS transistor with at least a first dopant; then, patterning said gate polysilicon to form a polysilicon transistor gate; then, implanting using a second shared MOS/resistor polysilicon implant level for simultaneously implanting said patterned polysilicon resistor, said gate polysilicon, and source and drain regions of said MOS transistor with at least a second dopant, and forming a metal silicide on a first and second portion of a top surface of said patterned polysilicon resistor to form said SIBLK poly resistor.
地址 Dallas TX US