发明名称 |
LOW LATENCY DIGITAL JITTER TERMINATION FOR REPEATER CIRCUITS |
摘要 |
A circuit for reducing jitter in a digital signal is provided, comprising a clock and data recovery stage operative to receive an input data signal and generate in response thereto a recovered data signal, a recovered clock signal, and an unfiltered interpolator code; a filter stage operative to receive the unfiltered interpolator code and generate in response thereto a filtered clock signal; and a memory component operative to receive the recovered data signal, the recovered clock signal, and the filtered clock signal; sample the recovered data signal using the recovered clock signal; store the resulting sampled bits; and generate an output data signal by selecting stored bits using the filtered clock signal. |
申请公布号 |
EP2737667(A1) |
申请公布日期 |
2014.06.04 |
申请号 |
EP20110869948 |
申请日期 |
2011.07.25 |
申请人 |
SEMTECH CANADA CORPORATION |
发明人 |
MARSHALL, ANDREW;WONG, HENRY;BENSOUDANE, ESSAID |
分类号 |
H04L12/70;H04L7/00 |
主分类号 |
H04L12/70 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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