Scalable distributed memory and I/O multiprocessor system

摘要

A multiprocessor system comprises at least one processing module, at least one I/O module, and an interconnect network to connect the at least one processing module with the at least one input/output module. In an example embodiment, the interconnect network comprises at least two bridges to send and receive transactions between the input/output modules and the processing module. The interconnect network further comprises at least two crossbar switches to route the transactions over a high bandwidth switch connection. Using embodiments of the interconnect network allows high bandwidth communication between processing modules and I/O modules. Standard processing module hardware can be used with the interconnect network without modifying the BIOS or the operating system. Furthermore, using the interconnect network of embodiments of the present invention is non-invasive to the processor motherboard. The processor memory bus, clock, and reset logic all remain intact.

主权项

1. An apparatus comprising:
a crossbar router; a bridge communicatively coupled to the crossbar router, the bridge including a data buffer to hold data associated with write request or read completion; and a Direct Memory Access (DMA) engine coupled to the crossbar router, wherein the bridge to obtain route information for converting a point-to-point request to an X-Link request.