Simulating a memory standard

摘要

An apparatus includes multiple first memory circuits, each first memory circuit being associated with a first memory standard, where the first memory standard defines a first set of control signals that each first memory circuit circuits is operable to accept. The apparatus also includes an interface circuit coupled to the first memory circuits, in which the interface circuit is operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard.

主权项

1. An apparatus comprising:
a plurality of first memory circuits, each first memory circuit of the plurality of first memory circuits being associated with a first memory standard, where the first memory standard defines a first set of control signals and timings that each first memory circuit of the plurality of first memory circuits is operable to accept; and an interface circuit coupled to the plurality of first memory circuits, the interface circuit being operable to emulate at least one second memory circuit, each second memory circuit being associated with a second different memory standard, wherein the second different memory standard defines a second set of control signals and timings that the at least one emulated second memory circuit is operable to accept; wherein the first memory standard and the second memory standard are different DDR dynamic random access memory (DRAM) memory standards.