High data rate transmitter and receiver

摘要

A high-speed transmitter and receiver are provided. In one embodiment, a transmitter comprises a baseband processor structured to receive data and to convert the data into a multiplicity of high and low signal values, with each high and low signal value having a first timing interval. A local oscillator generates a clock signal at a second timing interval and a digital circuit combines the high and low signal values with the clock signal to produce a transmission signal directly at a transmission frequency. A receiver is configured to receive the signal. This Abstract is provided for the sole purpose of complying with the Abstract requirement rules that allow a reader to quickly ascertain the subject matter of the disclosure contained herein. This Abstract is submitted with the explicit understanding that it will not be used to interpret or to limit the scope or the meaning of the claims.

主权项

1. A receiver comprising:
a front end configured to receive a communication signal that has a fractional bandwidth in a range between approximately 20 percent and approximately 200 percent; an analog to digital converter configured to directly convert the radio frequency signal into a data signal; a processing device configured to receive the data signal and to produce a plurality of data frames, determine a de-spreading code, and de-spread the data signal using the de-spreading code, wherein the de-spreading code is selected from a group consisting of: a 1-bit code, a 2-bit code, a 4-bit code, an 8-bit code, a 16-bit code, a 32-bit code, a 64-bit code, a 128-bit code, and a 256-bit code; and a medium access controller configured to receive the plurality of data frames and convert the data frames to data.