发明名称 |
Chip package and fabrication method thereof |
摘要 |
An embodiment of the invention provides a chip package, which includes: a semiconductor substrate having a device region; a package layer disposed on the semiconductor substrate; a spacing layer disposed between the semiconductor substrate and the package layer and surrounding the device region; and an auxiliary pattern having a hollow pattern formed in the spacing layer, a material pattern located between the spacing layer and the device region, or combinations thereof. |
申请公布号 |
US8741683(B2) |
申请公布日期 |
2014.06.03 |
申请号 |
US201314074519 |
申请日期 |
2013.11.07 |
申请人 |
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发明人 |
Huang Yu-Lung;Liu Tsang-Yu |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
1. A method for fabricating a chip package, comprising:
providing a package layer; forming a spacing material coating on the package layer; patterning the spacing material coating to form a spacing layer and an auxiliary pattern; providing a semiconductor wafer comprising a plurality of device regions and scribe lines between any two neighboring device regions; bonding the package layer to the semiconductor wafer, wherein the spacing layer surrounds the device region of the semiconductor wafer, and the auxiliary pattern comprises a hollow pattern formed in the spacing layer, a hollow pattern located on the scribe lines, a material pattern located between the spacing layer and the device region, or combinations thereof; and cutting the semiconductor wafer along the scribe lines to form a plurality of chip packages.
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地址 |
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