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1. A non-volatile semiconductor memory device comprising:
a semiconductor substrate; a memory string provided above the semiconductor substrate and comprising a plurality of memory transistors connected in series, the plurality of memory transistors being stacked above the semiconductor substrate; a control circuit configured to control a voltage applied to the memory string and a first capacitor provided above the semiconductor substrate; a first booster circuit comprising a plurality of first capacitors and configured to boost a voltage; a second booster circuit comprising a plurality of second capacitors each having a substantially constant capacitance and configured to boost a voltage; a first transistor; and a second transistor, the first capacitor comprising a plurality of first conductive layers and second conductive layers, the first conductive layers functioning as a first electrode of the first capacitor, the second conductive layers functioning as a second electrode of the first capacitor, the first conductive layers and the second conductive layers being arranged alternately in the direction substantially perpendicular to the semiconductor substrate, the first transistor being connected to the first conductive layers, the second transistor being connected to the second conductive layers, the control circuit being configured to control voltages of gates of the first transistor and the second transistor according to voltages of gates of the plurality of memory transistors, thereby changing a capacitance of the first capacitor, and the control circuit being configured to be capable of setting a third conductive layer to a floating state, the third conductive layer being one of the first conductive layers and the second conductive layers, the control circuit being configured to be capable of applying a first voltage to the first conductive layers and the second conductive layers except for the third conductive layer.
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