Integrated circuit including cross-coupled transistors having gate electrodes formed within gate level feature layout channels with gate contact position specifications

摘要

First and second PMOS transistors are defined over first and second p-type diffusion regions. First and second NMOS transistors are defined over first and second n-type diffusion regions. Each diffusion region is electrically connected to a common node. Gate electrodes are formed from conductive features that are each defined within any one gate level channel that is uniquely associated with and defined along one of a number of parallel gate electrode tracks. At least a portion of each of the first and second p-type diffusion regions are formed over a first common line of extent that extends perpendicular to the first parallel direction. The first and second n-type diffusion regions are formed in a spaced apart manner relative to the first parallel direction, such that no single line of extent that extends across the substrate perpendicular to the first parallel direction intersects both the first and second n-type diffusion regions.

主权项

1. An integrated circuit, comprising:
a gate electrode level region having a number of adjacently positioned gate electrode feature layout channels, each gate electrode feature layout channel extending lengthwise in a first direction and widthwise in a second direction perpendicular to the first direction, wherein each of the number of adjacently positioned gate electrode feature layout channels includes at least one gate level feature, each gate level feature having a first end located adjacent to a first line end spacing and a second end located adjacent to a second line end spacing, wherein each gate level feature forms an electrically conductive path extending between its first and second ends, wherein the gate electrode level region includes a first gate level feature that forms a gate electrode of a first transistor of a first transistor type and a gate electrode of a first transistor of a second transistor type, wherein the gate electrode level region includes a second gate level feature that forms a gate electrode of a second transistor of the first transistor type, wherein any transistor having its gate electrode formed by the second gate level feature is of the first transistor type, wherein the gate electrode level region includes a third gate level feature that forms a gate electrode of a second transistor of the second transistor type, wherein any transistor having its gate electrode formed by the third gate level feature is of the second transistor type, wherein the gate electrode of the second transistor of the second transistor type is substantially co-aligned with the gate electrode of the second transistor of the first transistor type along a first common line of extent in the first direction, and wherein the third gate level feature is separated from the second gate level feature by a first line end spacing as measured in the first direction, wherein the gate electrode level region includes a fourth gate level feature that forms a gate electrode of a third transistor of the first transistor type, wherein any transistor having its gate electrode formed by the fourth gate level feature is of the first transistor type, wherein the gate electrode level region includes a fifth gate level feature that forms a gate electrode of a third transistor of the second transistor type, wherein any transistor having its gate electrode formed by the fifth gate level feature is of the second transistor type, wherein the gate electrode of the third transistor of the second transistor type is substantially co-aligned with the gate electrode of the third transistor of the first transistor type along a second common line of extent in the first direction, and wherein the fifth gate level feature is separated from the fourth gate level feature by a second line end spacing as measured in the first direction, wherein the gate electrode level region includes a sixth gate level feature that forms a gate electrode of a fourth transistor of the first transistor type and a gate electrode of a fourth transistor of the second transistor type, wherein the gate electrodes of the second and third transistors of the first transistor type are positioned between the gate electrodes of the first and fourth transistors of the first transistor type in the second direction, wherein the gate electrodes of the second and third transistors of the second transistor type are positioned between the gate electrodes of the first and fourth transistors of the second transistor type in the second direction, wherein the second gate level feature is electrically connected to the fifth gate level feature through a first electrical connection that includes at least one gate level feature physically separate from each of the second and fifth gate level features, the first electrical connection including two contacts physically connected to the at least one gate level feature, wherein the first, second, third, and fourth transistors of the first transistor type are collectively separated from the first, second, third, and fourth transistors of the second transistor type by an inner portion of the gate electrode level region, wherein the gate electrode level region includes a first outer portion that extends in the first direction away from the first, second, third, and fourth transistors of the first transistor type collectively and away from the inner portion of the gate electrode level region, and wherein the gate electrode level region includes a second outer portion that extends in the first direction away from the first, second, third, and fourth transistors of the second transistor type collectively and away from the inner portion of the gate electrode level region; a first gate contact defined to physically contact the first gate level feature; a second gate contact defined to physically contact the second gate level feature; a third gate contact defined to physically contact the third gate level feature; a fourth gate contact defined to physically contact the fourth gate level feature; a fifth gate contact defined to physically contact the fifth gate level feature; and a sixth gate contact defined to physically contact the sixth gate level feature, wherein at least one of the second, third, fourth, and fifth gate contacts is positioned over either the first outer portion of the gate electrode level region or the second outer portion of the gate electrode level region, and wherein at least one of the two contacts of the first electrical connection is positioned over either the first outer portion of the gate electrode level region or the second outer portion of the gate electrode level region.