发明名称 LOGIC DIE AND OTHER COMPONENTS EMBEDDED IN BUILD-UP LAYERS
摘要 Embodiments of the present disclosure are directed towards package assemblies, as well as methods for forming package assemblies and systems incorporating package assemblies. A package assembly may include a substrate comprising a plurality of build-up layers, such as BBUL. In various embodiments, electrical routing features may be disposed on an outer surface of the substrate. In various embodiments, a primary logic die and a second die or capacitor may be embedded in the plurality of build-up layers. In various embodiments, an electrical path may be defined in the plurality of build-up layers to route electrical power or a ground signal between the second die or capacitor and the electrical routing features, bypassing the primary logic die.
申请公布号 WO2014081476(A1) 申请公布日期 2014.05.30
申请号 WO2013US48355 申请日期 2013.06.27
申请人 INTEL CORPORATION;KULKARNI, DEEPAK V.;MORTENSEN, RUSSELL K.;GUZEK, JOHN S. 发明人 KULKARNI, DEEPAK V.;MORTENSEN, RUSSELL K.;GUZEK, JOHN S.
分类号 H01L23/64;H01L25/16 主分类号 H01L23/64
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