发明名称 TIMESLOT MAPPING AND/OR AGGREGATION ELEMENT FOR DIGITAL RADIO FREQUENCY TRANSPORT ARCHITECTURE
摘要 A serial link interface unit includes serialized data stream interfaces configured to receive a serialized data stream having a data rate and set of timeslots; an aggregate serialized data stream interface configured to communicate an aggregate serialized data stream having aggregate data rate and plurality of aggregate timeslot sets each coming sequentially in time, wherein a second aggregate timeslot set comes after a first aggregate timeslot set; and wherein the serial link interface unit interleaves data from the different serialized data streams received at the plurality of first interfaces by mapping data from a first timeslot from each different serialized data stream to the first aggregate timeslot set in the aggregate serialized data stream and mapping data from a second timeslot from each different serialized data stream to the second aggregate timeslot set in the aggregate serialized data stream.
申请公布号 CA2892508(A1) 申请公布日期 2014.05.30
申请号 CA20132892508 申请日期 2013.11.26
申请人 ADC TELECOMMUNICATIONS, INC. 发明人 ZAVADSKY, DEAN;FORLAND, JODY;FISCHER, LARRY G.;WALA, PHILIP M.
分类号 H04L29/02;H04L29/10 主分类号 H04L29/02
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