MÉTODOS E EQUIPAMENTO PARA ESCALONAMENTO DE FREQUÊNCIA DINÂMICO DE LOOPS TRAVADOS POR FASE PARA MICROPROCESSADORES

摘要

A phase-locked loop employing a plurality of oscillator complexes is disclosed. The phase-locked loop includes a clock output and a plurality of oscillator complexes operable to generate output signals. The phase-locked loop further includes control logic which is configured to selectively couple an output signal of one of the plurality of oscillator complexes to the clock output.