| 摘要 |
<p>A hard macro (208, 308, 500) includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias (216, 318, 404) extending through the hard macro thickness from the top to the bottom. Also an integrated circuit (200, 300) having a top layer (202, 302), a bottom layer (210, 310) and at least one middle layer (206, 306), the top layer (202, 302) including a top layer conductive trace, the middle layer including a hard macro (208, 308) and the bottom layer (210, 310) including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via (216, 318, 404) extending through the hard macro (208, 308, 500).</p> |
