发明名称 |
ADAPTIVE EQUALIZER |
摘要 |
<p>An adaptive equalizer capable of suppressing an increase in circuit scale and an increase in operation clock frequency. An adaptive equalizer (100) performs an adaptive equalization process on a time-region signal in a frequency region. A signal converter (200) has: a first wide-bit memory (201) capable of reading/writing a plurality of sample signals; a first register group (202) comprising a plurality of registers capable of accessing the first wide-bit memory (201); a butterfly computation unit group (204) comprising a plurality of butterfly computation units; and a first connection switching unit (203) for switching the state of connection between the plurality of registers and the plurality of butterfly computation units.</p> |
申请公布号 |
EP2733622(A1) |
申请公布日期 |
2014.05.21 |
申请号 |
EP20120841483 |
申请日期 |
2012.06.29 |
申请人 |
PANASONIC CORPORATION |
发明人 |
YOMO, HIDEKUNI;MATSUOKA, AKIHIKO;MARUYAMA, ATSUSHI |
分类号 |
G06F17/14;H04B7/005;H04J11/00;H04L25/03;H04L27/01;H04L27/26 |
主分类号 |
G06F17/14 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|