发明名称 CLOCKED AND-OR GATE
摘要 FIELD: information technology.SUBSTANCE: clocked AND-OR gate comprises a p-type pre-charge transistor 1, an n-type clock transistor 2, a p-type clock transistor 3, a p-type logic transistor 4 and a logic unit, having switch circuits 6-7, connected in parallel between the output 8 of the logic unit 5 and a clock bus 9. Each switch circuit consists of series-connected n-type transistors, whose gates are connected to logic inputs 10 of the logic gate.EFFECT: low power consumption.1 dwg
申请公布号 RU2515702(C1) 申请公布日期 2014.05.20
申请号 RU20120143813 申请日期 2012.10.15
申请人 FEDERAL'NOE GOSUDARSTVENNOE BJUDZHETNOE UCHREZHDENIE NAUKI INSTITUT PROBLEM UPRAVLENIJA IM. V.A. TRAPEZNIKOVA ROSSIJSKOJ AKADEMII NAUK 发明人 LEMENTUEV VLADIMIR ANUFRIEVICH
分类号 H03K19/20 主分类号 H03K19/20
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