| 摘要 |
PROBLEM TO BE SOLVED: To solve a problem, where as the memory capacity increases, the length of a read bit line in a memory array increases and the read speed decreases due to such as the parasitic capacitance of the read bit line.SOLUTION: The source potential of a transistor for reading memory cells is controlled by changing the voltage level of a source control line SL01, and data of the memory cells is selectively read to read bit lines RB0 and RB1. A source control line SL on a selected column is set to a Lo level and a source control line SL on an unselected column is set to a Hi level. A reference voltage generation circuit VRG discharges the electric charges of read bit lines RB2 and RB3 by the source control line SL01, and generates a reference voltage Vref of a level between a pre-charge level and a bit line potential during the reading of "L." Differential sense amplifiers DAM1 and DAM2 amplify and output the read data and reference voltage Vref. |
