发明名称 |
LOW CAPACITANCE TRANSIENT VOLTAGE SUPPRESSOR (TVS) WITH REDUCED CLAMPING VOLTAGE |
摘要 |
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer. |
申请公布号 |
US2014134825(A1) |
申请公布日期 |
2014.05.15 |
申请号 |
US201414157416 |
申请日期 |
2014.01.16 |
申请人 |
ALPHA & OMEGA SEMICONDUCTOR INCORPORATED |
发明人 |
GUAN LINGPENG;BOBDE MADHUR;BHALLA ANUP;HU JUN;ENG WAYNE F. |
分类号 |
H01L21/822;H01L21/265;H01L21/762 |
主分类号 |
H01L21/822 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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