发明名称 THERMAL PERFORMANCE OF LOGIC CHIP IN A PACKAGE-ON-PACKAGE STRUCTURE
摘要 Embodiments of the invention provides an IC system in which low-power chips can be positioned vertically proximate high-power chips without suffering the effects of overheating. In one embodiment, the IC system includes a first substrate, a high-power chip disposed on a first side of the first substrate, a thermal conductive pad disposed on a second side of the first substrate, one or more thermal conductive features formed in the first substrate, wherein the thermal conductive features thermally connect the high-power chip and the thermal conductive pad, and a heat sink attached to a surface of the thermal conductive pad, wherein the heat sink is in thermal communication with the thermal conductive pad. By having thermal conductive features formed through the first substrate to thermally connect the high-power chip and the thermal conductive pad, heat generated by the high-power chip can be effectively dissipated into the heat sink.
申请公布号 US2014131847(A1) 申请公布日期 2014.05.15
申请号 US201213673592 申请日期 2012.11.09
申请人 NVIDIA CORPORATION 发明人 YEE ABRAHAM F.;CHIPALKATTI JAYPRAKASH;KALCHURI SHANTANU
分类号 H01L23/495 主分类号 H01L23/495
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