发明名称 Correlation-based background calibration for reducing inter-stage gain error and non-linearity in pipelined analog-to-digital converters
摘要 A method and a corresponding device for calibrating a pipelined analog-to-digital converter (ADC) involve injecting a randomly determined amount of dither into one of a flash component and a multiplying digital-to-analog converter (MDAC) in at least one stage in the ADC. For each stage of the at least one stage a correlation procedure is performed to estimate, based on an output of the ADC, an amount of gain experienced by the injected dither after propagating through the stage. The stage is then calibrated based on its respective gain estimate.
申请公布号 US8723707(B2) 申请公布日期 2014.05.13
申请号 US201213560226 申请日期 2012.07.27
申请人 ALI AHMED MOHAMED ABDELATTY;ANALOG DEVICES, INC. 发明人 ALI AHMED MOHAMED ABDELATTY
分类号 H03M1/10 主分类号 H03M1/10
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