发明名称 MEMORY DEVICE, ARITHMETIC PROCESSING UNIT, AND CACHE MEMORY CONTROL METHOD
摘要 PROBLEM TO BE SOLVED: To provide a memory device that strikes a balance between maintaining performance and reducing power consumption.SOLUTION: A memory device includes: a plurality of ways; a register that holds a history of access to the plurality of ways; and a way control unit that selects one or a plurality of ways out of the plurality of ways according to an access request and the access history, causes the selected ways to operate, and disables the operation of ways other than the selected ways. The way control unit dynamically changes the number of ways to be selected, according to the access request.
申请公布号 JP2014085890(A) 申请公布日期 2014.05.12
申请号 JP20120235109 申请日期 2012.10.24
申请人 FUJITSU LTD 发明人 SHIROHIGE YUJI
分类号 G06F12/08 主分类号 G06F12/08
代理机构 代理人
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