发明名称 |
SEMICONDUCTOR DEVICE WITH REDUCED MILLER CAPACITANCE AND FABRICATION METHOD THEREOF |
摘要 |
A semiconductor transistor device includes an epitaxial layer grown on a semiconductor substrate; an ion well with a junction depth in the epitaxial layer; a gate trench with a depth shallower than the junction depth in the ion well; a recess at the bottom of the gate trench; a gate oxide layer at surface of the gate trench and in the recess to form a protruding tip structure; a gate in the gate trench; and a drain extension region between the gate trench and the epitaxial layer. |
申请公布号 |
US2014124853(A1) |
申请公布日期 |
2014.05.08 |
申请号 |
US201314051451 |
申请日期 |
2013.10.11 |
申请人 |
ANPEC ELECTRONICS CORPORATION |
发明人 |
LIN YUNG-FA |
分类号 |
H01L29/78 |
主分类号 |
H01L29/78 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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