发明名称 |
System and method for soft error detection in memory devices |
摘要 |
A system for detecting soft errors in a memory device includes a latch, a master flip-flop and a slave flip-flop. The latch receives input data (control and/or address signals) at the beginning of a memory operation in response to a rising edge of a first clock signal. The output of the latch is provided to the master flip-flop. The master flip-flop continuously receives and stores the latch output during the memory operation based on a second clock signal. The slave flip-flop receives and stores the output of the master flip-flop at the end of the memory operation based on the second clock signal. A comparator compares the input data with the output of the slave flip-flop to detect soft errors that occur during the memory operation. |
申请公布号 |
US8717829(B2) |
申请公布日期 |
2014.05.06 |
申请号 |
US201213532804 |
申请日期 |
2012.06.26 |
申请人 |
SHARMA ASHISH;EIFERT JAMES B.;GUPTA AMIT KUMAR;LISTON THOMAS W.;REFAELI JEHODA;FREESCALE SEMICONDUCTOR, INC. |
发明人 |
SHARMA ASHISH;EIFERT JAMES B.;GUPTA AMIT KUMAR;LISTON THOMAS W.;REFAELI JEHODA |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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