发明名称 |
Successive approximation register analog-to-digital converter |
摘要 |
A successive approximation register analog-to-digital converter is provided which includes first and second capacitor arrays configured to generate first and second level voltages, respectively; a comparator configured to compare the first and second level voltages to output a comparison signal; SAR logic configured to generate a digital signal in response to the comparison signal; and a variable common mode selector configured to compare a first analog input voltage and a common mode voltage and to supply one of the first analog input voltage and the common mode voltage to top plates of the first and second capacitor arrays according to a comparison result. |
申请公布号 |
US8717221(B2) |
申请公布日期 |
2014.05.06 |
申请号 |
US201313763532 |
申请日期 |
2013.02.08 |
申请人 |
ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE |
发明人 |
JEON YOUNG-DEUK;ROH TAE MOON;KWON JONG-KEE |
分类号 |
H03M1/38 |
主分类号 |
H03M1/38 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|