发明名称 |
Dual-leadframe multi-chip package and method of manufacture |
摘要 |
A dual-leadframe multi-chip package comprises a first leadframe with a first die pad, and a second leadframe with a second die pad; a first chip mounted on the first die pad functioning as a high-side MOSFET and second chip mounted on the second die pad functioning as a low-side MOSFET. The package may further comprises a bypass capacity configured as a third chip mounted on the first die pad or integrated with the first chip. The package may further comprise a three-dimensional connecting plate formed as an integrated structure as the second die pad for electrically connecting a top contact area of the first chip to a bottom contact area of the second chip. A top connecting plate connects a top contact area of the second chip and a top contact area of the third chip to an outer pin of the first leadframe. |
申请公布号 |
US8709867(B2) |
申请公布日期 |
2014.04.29 |
申请号 |
US201213411990 |
申请日期 |
2012.03.05 |
申请人 |
LIU KAI;SHI LEI;LU JUN;BHALLA ANUP;ALPHA & OMEGA SEMICONDUCTOR INC. |
发明人 |
LIU KAI;SHI LEI;LU JUN;BHALLA ANUP |
分类号 |
H01L21/00 |
主分类号 |
H01L21/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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