发明名称 |
Configurable source based/requestor based error detection and correction for soft errors in multi-level cache memory to minimize CPU interrupt service routines |
摘要 |
This invention is a memory system with parity generation which selectively forms and stores parity bits of corresponding plural data sources. The parity generation and storage depends upon the state of a global suspend bit and a global enable bit, and parity detection/correction corresponding to each data source. |
申请公布号 |
US8707127(B2) |
申请公布日期 |
2014.04.22 |
申请号 |
US201113243335 |
申请日期 |
2011.09.23 |
申请人 |
TRAN JONATHAN (SON) HUNG;CHACHAD ABHIJEET ASHOK;DAMODARAN RAGURAM;GURRAM KRISHNA CHAITHANYA;TEXAS INSTRUMENTS INCORPORATED |
发明人 |
TRAN JONATHAN (SON) HUNG;CHACHAD ABHIJEET ASHOK;DAMODARAN RAGURAM;GURRAM KRISHNA CHAITHANYA |
分类号 |
H03M13/00 |
主分类号 |
H03M13/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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