发明名称 |
N/P boundary effect reduction for metal gate transistors |
摘要 |
The present disclosure provides a method of fabricating a semiconductor device. The method includes forming a plurality of dummy gates over a substrate. The dummy gates extend along a first axis. The method includes forming a masking layer over the dummy gates. The masking layer defines an elongate opening extending along a second axis different from the first axis. The opening exposes first portions of the dummy gates and protects second portions of the dummy gates. A tip portion of the opening has a width greater than a width of a non-tip portion of the opening. The masking layer is formed using an optical proximity correction (OPC) process. The method includes replacing the first portions of the dummy gates with a plurality of first metal gates. The method includes replacing the second portions of the dummy gates with a plurality of second metal gates different from the first metal gates. |
申请公布号 |
US8703595(B2) |
申请公布日期 |
2014.04.22 |
申请号 |
US201113299152 |
申请日期 |
2011.11.17 |
申请人 |
CHUANG HAK-LAY;KUO CHENG-CHENG;TSAI CHING-CHE;ZHU MING;YOUNG BAO-RU;TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
CHUANG HAK-LAY;KUO CHENG-CHENG;TSAI CHING-CHE;ZHU MING;YOUNG BAO-RU |
分类号 |
H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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