发明名称 |
Static analysis of VLSI reliability |
摘要 |
A circuit verifier having an input interface configured to receive descriptions of integrated circuits and a processing unit configured to scan through a description of an integrated circuit received through the input interface in order to identify clock domain crossings in the circuit and to provide a numerical score for each of the identified clock domain crossings. |
申请公布号 |
US8707229(B1) |
申请公布日期 |
2014.04.22 |
申请号 |
US201113191487 |
申请日期 |
2011.07.27 |
申请人 |
DOBKIN ROSTISLAV (REUVEN);BROOK LEONID;VSYNC CIRCUIT, LTD. |
发明人 |
DOBKIN ROSTISLAV (REUVEN);BROOK LEONID |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|